1. Field of the Invention
The present invention relates to a semiconductor device for MOS transistors or the like and a manufacturing method thereof, and more particularly to a semiconductor device suitably applicable for high-performance CMOS transistors or the like and a manufacturing method thereof.
2. Description of the Related Art
In recent years, request for further miniaturization of CMOS transistors has been rising, propelling efforts to shorten the gate length in order to meet this request. However, pursuit of shorter gate lengths brings about a problem of the so-called short-channel effect. Therefore, methods have been devised to suppress the short-channel effect by increasing the impurity concentration in the channel region. However, increasing the impurity concentration in the channel region causes degradation of carrier mobility due to impurity scattering, which may result in obstruction to increase the drive current. As thus, when attempting to shorten the gate length, the request for suppressing the short-channel effect and the request for preventing degradation of carrier mobility are in a trade-off relation.
To address the above-stated problems, so-called epi channel transistors or retrograde channel transistors have been proposed as an ideal device structure which does not bring about mobility degradation, while suppressing the short-channel effect. For such transistors, the surface layer of the channel region is kept having an extremely low impurity concentration or in a non-doped state, whereas lower layers have a higher impurity concentration. In such transistors, mobility degradation due to impurity scattering is suppressed because carriers move in the inversion layer formed on the surface layer, while elongation of drain depletion layer is prevented by the highly doped lower layer under the surface layer, resulting in suppression of the short channel effect.
[Patent Document 1] Japanese Patent Application Laid-open No. 2004-153246
However, although the above-stated transistor structure is ideal as a configuration model of a device, currently there is no preferable approach devised for realizing such a structure. In particular, for the epi channel transistor, such an ideal step-profile of impurity concentration has been extremely difficult to realize, because impurities are diffused during activation annealing or other heat processes.